1. Field of the Invention
The present invention relates generally to phase-locked loops (PLL) and specifically to a fractional-N phase-locked loop.
2. Related Art
Radio, telecommunications, computers, and other electronic applications for signal stabilization, signal detection, frequency demodulation, or bit synchronization to provide some examples widely use phase-locked loops (PLL). These applications may include frequency synthesizers for digitally-tuned radio receivers and transmitters, the demodulation of frequency modulated (FM) and amplitude modulated (AM) signals, the recovery of small signals that otherwise would be lost in noise, the recovery of clock timing information from a data stream, clock multipliers in microprocessors, or dual-tone multi-frequency (DTMF) decoders, modems, and other tone decoders for remote control and telecommunications to provide some examples.
The PLL is a closed-loop feedback control system that generates a signal in relation to the frequency and phase of a reference signal. In their most basic form, PLL mechanisms may be implemented as either analog or digital circuits using a phase/frequency detector (PFD), a charge pump, a voltage controlled oscillator (VCO), and a feedback path. The PFD produces an error signal by comparing a frequency and a phase of the VCO to a frequency and a phase of the reference signal. The charge pump generates a reference or tuning voltage to be applied to the VCO based on the error signal. The PLL responds to the tuning voltage by automatically raising or lowering an output frequency of the VCO until the frequency and a phase of the output frequency of the VCO is matched with the frequency and the phase of the reference signal. An optional loop filter may remove undesirable noise from the tuning voltage.
The PLL may also include frequency divider in a feedback configuration between the VCO and the PFD. The frequency divider may divide the output frequency of the VCO by a corresponding value depending on the frequency of the reference signal. The PLL may be implemented as a integer PLL, including an integer divider, to divide the VCO output frequency by an integer multiple of the frequency of the reference signal. However, in some applications it may be desirable to cause the VCO to output a frequency that is a fractional multiple of the reference signal. In this situation, a fractional-N PLL is necessary to divide the output frequency of the VCO by a fractional multiple.
Various techniques are used to implement a fractional-N PLL frequency divider. Conventional methods, such as using a programmable pulse swallowing counter or various techniques of modulation of the feedback divider's integer value, to yield an effective non-integer value, may generate additional phase noise and time domain jitter at the output of the PLL. Therefore, what is needed is a PLL having a fractional frequency divider to reduce the phase noise and the time domain jitter at the output of the fractional-N PLL.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.